半導體 Semiconductor

CoWos Three Types MindMap (Chillyin illustrated, 2025)

參考文獻 reference:

Taiwan Semiconductor Manufacturing Company. (n.d.). CoWoS®. TSMC 3DFabric™. Retrieved Feb 11, 2025, from https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm

https://3dfabric.tsmc.com/chinese/dedicatedFoundry/technology/cowos.htm 

#Chillyin的半導體觀察筆記 🌹 

#ChillyinSEMI 

Integrator: Chilly Chiou 《CHILLYIN LTD.》

 CoWoS 三種類型簡述及比較  

簡言之

#CoWoSS 性能最佳但成本最高

#CoWoSR 成本最低但性能較低

#CoWoSL 則兼顧性能和成本，並提供更高的 HBM 堆疊數量和尺寸彈性

台積電的 CoWoS

#先進封裝 技術主要有三種類型：CoWoS-S、CoWoS-R 和 CoWoS-L，它們的主要區別在於

#中介層 使用的材料。

1. CoWoS-S 

中介層：矽中介層 (Silicon Interposer)

特性：性能最佳，但成本最高。

矽中介層利用

#矽穿孔技術 ，提供高密度互連和良好的散熱性能。

適合 AI 伺服器晶片、高效能運算 (HPC) 產品，例如 NVIDIA Hopper H100、H200 和 AMD MI300。

缺點：矽材料較脆弱，尺寸放大後良率難以提升。

2. CoWoS-R 

中介層：重分佈層 (RDL Interposer)

特性：成本較 CoWoS-S 低，封裝尺寸彈性較高。

RDL 中介層由

#聚合物和銅線 構成，具備較高的彈性，允許封裝尺寸進一步擴展。

適合網通設備、邊緣 AI 等產品。

缺點：性能不如 CoWoS-S。

3. CoWoS-L 

中介層：重分佈層 + 局部矽互聯 (LSI)

特性：結合 CoWoS-S 和 CoWoS-R 的優點，成本介於兩者之間。

局部區域使用矽中介層 (LSI) 進行高速互連，其他區域使用

#重佈線層 ，提供高度靈活的整合能力。

可堆疊的 HBM 數量較 CoWoS-S 多，最多可達 12 顆。

適合 NVIDIA Blackwell 系列晶片，例如 B100、B200、B300 和 GB200。 

 CoWoS - A Brief Introduction and ComparisonOfCoWos Three Types 

In short, CoWoS-S offers the best performance but comes at the highest cost. CoWoS-R is the most cost-effective but has lower performance. CoWoS-L balances performance and cost while providing higher HBM stacking capacity and size flexibility.

TSMC's CoWoS advanced packaging technology mainly comprises three types: CoWoS-S, CoWoS-R, and CoWoS-L. Their main difference lies in the materials used for the interposer. 

●CoWoS-S 

Interposer: Silicon Interposer 

Features: Best performance, but highest cost.

Utilizes silicon vias to provide high-density #interconnect and good thermal performance. 

Suitable for AI server chips and high-performance computing (HPC) products, such as NVIDIA Hopper H100, H200, and AMD MI300. 

Drawbacks: Silicon material is relatively fragile, making it difficult to improve yield when scaling up the size.

●CoWoS-R 

Interposer: Redistribution Layer (#RDL Interposer)

Features: Lower cost and higher package size flexibility compared to CoWoS-S.

The RDL interposer is composed of #polymers and #copper wires, offering high flexibility and allowing for further expansion of package size.

Suitable for network communication equipment and edge AI products.

Drawbacks: Performance is not as good as CoWoS-S.

●CoWoS-L 

Interposer: Redistribution Layer + Local Silicon Interconnect (#LSI)

Features: Combines the advantages of CoWoS-S and CoWoS-R, with the cost falling between the two.

Uses LSI for high-speed interconnect in local areas and redistribution layers in other areas, providing highly flexible integration capabilities.

Offers higher HBM stacking capacity than CoWoS-S, up to 12 chips.

Suitable for NVIDIA Blackwell series chips, such as B100, B200, B300, and GB200. 

晶片戰爭下的科技競逐 (Chip War: Tech Race & Reshaping) MindMap

參考文獻 reference:

Ko, Justin (2025). TSMC, SMIC, and the Global Chip War.

Hübner, Jörg (2025). Why Is the Chip Industry So Special? In Business and Policy Challenges of Global Uncertainty (pp. 235-251).

Ryu, Yongwook (2025). Chips on the Deck: US-China Rivalry and Reorganizing the Supply Chains of Semiconductors. In N. Hung Son & N. Thi Lan Anh (Eds.), The South China Sea: The Geo-political Epicenter of the Indo-Pacific? (Chapter 8). Springer, Singapore.

 晶片戰爭下的科技競逐 

當前全球科技發展的核心，無疑聚焦於半導體產業。這場被喻為「晶片戰爭」的競賽，不僅是技術實力的較量，更深刻地重塑了全球供應鏈格局，並與複雜的地緣政治緊密交織。綜合近期多份研究報告，我們可以清晰地看到幾個關鍵的科技發展趨勢、重點討論議題以及被特別強調的觀點。

一、 技術自主與「蠻力突破」：非對稱的創新路徑

在美國對中國半導體產業實施嚴格出口管制，特別是限制先進製程設備（如ASML的EUV光刻機）的背景下，中國的晶片製造商如中芯國際（SMIC）正試圖以非傳統方式突圍 。Justin Ko在其研究中指出，中芯國際在2023年據報導成功為華為Mate 60生產7奈米晶片（麒麟9000s），並可能正利用舊有的DUV（深紫外光刻）工具，透過自對準四重圖案化（SAQP）等「蠻力」手段，嘗試生產5奈米晶片 。

這一趨勢的重點在於：

• 規避制裁的創新驅動力： 出口限制反而可能激發了在現有技術框架下尋求極限突破的動機 。若非EUV設備取得受限，企業不太可能投入巨大資源去優化效率較低、速度較慢的生產技術。

• 供應鏈的「紅色」自主化： 中芯的技術突破，即使在效率和成本上不及主流EUV方案，其地緣政治意義重大。它增強了中國本土晶片消費者（如華為、阿里巴巴）使用國產晶片的意願，以降低對外國供應商（如NVIDIA、TSMC）的依賴，並減輕未來遭受更嚴厲制裁的風險 。這將直接推動一個更能抵禦外部限制的「紅色晶片供應鏈」的形成 。

• 非對稱競爭： 這種「蠻力突破」雖然在技術指標上可能追趕，但在生產效率、成本和良率方面，與台積電等採用最新EUV技術的領導者相比，仍存在巨大差距。然而，其戰略價值在於展示技術潛力和部分自主能力。

二、 全球供應鏈的專業化、集中化及其脆弱性

Jörg Hübner在其研究摘要中強調，微晶片是幾乎所有用電產品的基礎成分，不僅革新了資訊處理和通訊，也在再生能源系統和穩定電網中扮演不可或缺的角色。先進晶片的生產具有高度軍事意義，支持基於AI的先進武器系統，從而產生地緣政治影響。

Yongwook Ryu也指出，半導體產業擁有全球最複雜、高度整合的供應鏈之一，不同任務由不同地區的不同參與者執行 。這種高度專業化和全球價值鏈上的整合，使得關鍵的價值鏈活動集中在特定地理區域：

• 設計與IP： 美國和英國在電子設計自動化（EDA）工具和核心IP方面佔據主導 。

• 製造設備： 美國、日本和歐洲是半導體製造設備的主要供應商 。ASML的EUV光刻機是先進製程的瓶頸技術 。

• 晶圓代工： 最先進的製造設施集中在東亞，特別是台灣（台積電）和韓國（三星）。台積電在全球晶圓代工市場長期佔據超過50%的份額，甚至接近67% 。

• 封裝測試（OSAT）： 中國在後端封測領域佔有約20%的市場份額，但此環節相對容易被替代 。

這種高度集中和專業化的結果是，全球晶片價值鏈變得高度耦合且缺乏彈性，難以承受重大干擾，正如COVID-19疫情期間所見證的那樣。Hübner的摘要指出，這促使美國、歐洲以及東亞的市場領導者紛紛試圖提升本地產能。

三、 地緣政治對決下的供應鏈重組與「友岸外包」

美中之間的戰略競爭已從貿易戰轉向科技競爭，半導體領域首當其衝 。Ryu在其研究中詳細闡述了美國試圖利用其在晶片生產前端（軟體、EDA、IP）的市場主導地位以及其科技盟友網絡，迫使中國與全球晶片供應鏈「脫鉤」或顯著降低其地位 。

美國的半導體政策目標有二：

1. 建立本土安全供應鏈： 透過《晶片法案》(Chips for America Act) 和《美國晶圓代工法案》(American Foundries Act) 等產業政策，提供稅收優惠和資金支持，鼓勵在美國本土投資設廠，提升本土製造能力 。美國的製造產能已從1990年的37%下降到2010年的13%，預計到2030年可能進一步降至10% 。

2. 限制中國的技術進步： 將華為、中芯國際等中國企業列入實體清單，限制其獲取美國技術和先進設備（如EUV）。出口管制範圍也從最初的邏輯晶片擴展到記憶體晶片，並從先進製程延伸至中階製程 。

與此同時，美國積極推動與歐洲和亞洲盟友的合作，即所謂的「友岸外包」(friend-shoring)，加強與韓國、台灣、日本、荷蘭、德國等的夥伴關係 。台積電和三星應美國政府要求，已分別承諾在亞利桑那州和德州建廠 。

四、 領導者與企業文化：塑造產業格局的無形力量

Ko的著作特別強調了企業領導者及其背景對公司發展軌跡的深遠影響。他詳細比較了台積電創辦人張忠謀 (Morris Chang) 和中芯國際創辦人張汝京 (Richard Chang) 的相似背景（均出生於江南，赴美接受工程教育，曾任職於德州儀器）以及他們各自的經營理念和人生抉擇 。

• 張忠謀與台積電的「純晶圓代工」模式： 張忠謀開創並堅守「純晶圓代工」模式，不與客戶競爭晶片設計，贏得了全球設計公司的信任 。其嚴格的管理（如對保密的高度重視）和對技術創新的持續投入（如支持林本堅的浸潤式光刻技術和胡正明的FinFET技術商業化）是台積電成功的關鍵 。台積電的反週期投資策略也使其能在經濟下行時擴大產能，鞏固領先地位 。

• 張汝京的「紅色供應鏈」夢想與SMIC的挑戰： 張汝京則帶有更強的家國情懷，致力於在中國大陸建立自主的半導體產業 。他以極度注重成本控制和優先扶持本土供應商著稱 。儘管SMIC因與台積電的專利訴訟遭遇重挫（張汝京因此辭職），但其後在政府支持和後續領導者（如蔣尚義、邱慈雲、梁孟松等同樣具有台灣背景和美國教育經歷的工程師）的努力下，SMIC依然是中國大陸半導體自主化最重要的希望 。

五、 未來的競賽：技術創新、效率與地緣政治的角力

Ryu總結道，美中之間的晶片競賽將日益激烈，其動態類似於軍備競賽，雙方都關注相對收益，使之成為一場零和遊戲 。美國憑藉其盟友網絡在重組供應鏈方面具有成本優勢，而中國則面臨被孤立的風險，儘管其會努力尋求自主並分化美國的同盟 。

最終，誰能主導晶片領域，不僅取決於技術的先進性，更取決於創新能力、生產效率以及在複雜地緣政治環境中的運籌帷幄 。各國政府必須與企業密切協商，制定長期的研發和產業策略 。正如張忠謀所言，在其任內從未遇到的「友岸外包」、「境內製造」等地緣政治挑戰，已成為當前領導者必須面對的現實 。而張汝京的經歷則顯示，即便面臨制裁和訴訟，強烈的使命感和政府支持也能催生出堅韌的追趕者。

這場晶片戰爭的結果，將深遠影響全球科技版圖和國際力量的平衡。

 The Tech Race in the Chip War 

The core of current global technological development undoubtedly revolves around the semiconductor industry. This competition, often dubbed the "Chip War," is not merely a contest of technical prowess but is also profoundly reshaping global supply chain structures and is intricately intertwined with complex geopolitical dynamics. Synthesizing insights from several recent research reports, we can clearly identify key technological development trends, focal points of discussion, and particularly emphasized perspectives.

I. Technological Self-Reliance and "Brute Force Breakthroughs": Asymmetric Paths to Innovation

Against the backdrop of strict U.S. export controls on China's semiconductor industry, particularly restrictions on advanced process equipment like ASML's EUV lithography tools, Chinese chip manufacturers such as Semiconductor Manufacturing International Corporation (SMIC) are attempting to achieve breakthroughs through unconventional means. Justin Ko notes in his research that SMIC reportedly succeeded in producing a 7-nanometer chip, the Kirin 9000s, for Huawei's flagship Mate 60 phone in 2023, and may now be on the verge of producing 5nm chips using older deep ultraviolet (DUV) tools through processes like Self-Aligned Quadruple Patterning (SAQP) – a "brute force" approach.

Key aspects of this trend include:

• Innovation Driven by Sanctions Circumvention: Export restrictions may have ironically spurred motivation to seek extreme breakthroughs within existing technological frameworks. If EUV tools were readily available, it's unlikely a company would invest so much effort in optimizing inefficient and slower production techniques.

• "Red" Autonomous Supply Chain: SMIC's technological advancements, even if less efficient and cost-effective than mainstream EUV solutions, carry significant geopolitical weight. They increase the likelihood of Chinese domestic chip consumers like Huawei or Alibaba using domestically produced chips and DUV-based techniques to reduce dependence on foreign suppliers like Nvidia and TSMC, thereby mitigating their risk of future sanctions. This will directly contribute to the creation of a self-reliant "red chip supply chain" more resilient to external restrictions.

• Asymmetric Competition: While these "brute force breakthroughs" might catch up in terms of technical specifications, they still face a significant gap in production efficiency, cost, and yield compared to leaders like TSMC, which use the latest EUV technology. However, their strategic value lies in demonstrating technological potential and a degree of self-sufficiency.

II. Specialization, Concentration, and Vulnerability of Global Supply Chains

Jörg Hübner, in his research abstract, emphasizes that microchips are fundamental components in almost all electrically powered products, revolutionizing information processing and communication, and serving as indispensable parts in renewable energy systems and stable power grids. The production of leading-edge chips is of high military importance, supporting advanced weapon systems using AI, thus having geopolitical implications.

Yongwook Ryu also points out that the semiconductor industry possesses one of the most complex and highly integrated supply chains globally, with different tasks performed by various actors in different locales. This high degree of specialization and integration along the global value chain has led to the concentration of essential activities in specific geographical regions:

• Design & IP: The U.S. and UK dominate in Electronic Design Automation (EDA) tools and core IPs.

• Manufacturing Equipment: The U.S., Japan, and Europe are major suppliers of semiconductor manufacturing equipment. ASML's EUV lithography machines are a bottleneck technology for advanced processes.

• Foundry Services: The most advanced manufacturing facilities are concentrated in East Asia, particularly Taiwan (TSMC) and South Korea (Samsung). TSMC has long held over 50% of the global foundry market share, reaching nearly 67%.

• Assembly, Testing, and Packaging (OSAT): China holds about 20% of the market share in the back-end OSAT segment, but this segment is relatively easier to replace.

The result of this high concentration and specialization is that the global chip value chain has become tightly coupled and less flexible, making it vulnerable to major disruptions, as witnessed during the COVID-19 pandemic. Hübner's abstract notes that this has prompted various governments from the U.S. and Europe, as well as incumbent market leaders in East Asia, to attempt to advance their local production capacities.

III. Supply Chain Reorganization and "Friend-Shoring" Amidst Geopolitical Rivalry

The strategic rivalry between the U.S. and China has shifted from a trade war to technological competition, with the semiconductor sector at the forefront. Ryu, in his research, details how the U.S. is attempting to leverage its market dominance in the front-end of chip production (software, EDA, IP) and its extensive network of tech-capable allies to force China to "decouple" from global chip supply chains or significantly reduce its role.

U.S. semiconductor policy has two main goals:

1. Establishing a Secure Domestic Supply Chain: Through industrial policies like the Chips for America Act and the American Foundries Act, the U.S. provides tax incentives and funding to encourage investment in domestic manufacturing facilities, aiming to boost its own production capacity. U.S. manufacturing capacity declined from 37% of global capacity in 1990 to 13% in 2010, and is projected to fall further to 10% by 2030.

2. Restricting China's Technological Advancement: Placing Chinese companies like Huawei and SMIC on entity lists limits their access to American technology and advanced equipment (like EUV). Export controls have expanded from logic chips to memory chips and from advanced to mid-tier processes.

Concurrently, the U.S. is actively promoting "friend-shoring," strengthening partnerships with allies in Europe and Asia, including South Korea, Taiwan, Japan, the Netherlands, and Germany. TSMC and Samsung, at the U.S. government's request, have committed to building fabs in Arizona and Texas, respectively.

IV. Leadership and Corporate Culture: Intangible Forces Shaping the Industry

Ko's work particularly highlights the profound impact of corporate leaders and their backgrounds on their companies' trajectories. He draws detailed comparisons between TSMC founder Morris Chang and SMIC founder Richard Chang, noting their similar backgrounds (both born in the Jiangnan region, U.S.-educated engineers, former Texas Instruments employees) yet distinct business philosophies and life choices.

• Morris Chang and TSMC's "Pure-Play Foundry" Model: Morris Chang pioneered and adhered to the pure-play foundry model, refraining from chip design to avoid competing with customers, thereby earning the trust of global design houses. His stringent management (e.g., extreme emphasis on confidentiality) and continuous investment in technological innovation (such as supporting Burn-Jeng Lin's immersion lithography and Chenming Hu's FinFET commercialization) were key to TSMC's success. TSMC's counter-cyclical investment strategy also allowed it to expand capacity during economic downturns, solidifying its lead.

• Richard Chang's "Red Supply Chain" Dream and SMIC's Challenges: Richard Chang was driven by a stronger sense of patriotism, dedicating himself to building an indigenous semiconductor industry in Mainland China. He was known for his intense focus on cost control and prioritizing domestic suppliers. Although SMIC faced a major setback due to a patent lawsuit with TSMC (which led to Richard Chang's resignation), with government support and the efforts of subsequent leaders (many of whom, like Jiang Shangzhou, Chiu Tzi-yun, and Liang Mong-song, also had Taiwanese backgrounds and U.S. educations), SMIC remains Mainland China's best hope for semiconductor self-sufficiency.

V. The Future Contest: A Tug-of-War of Innovation, Efficiency, and Geopolitics

Ryu concludes that the U.S.-China chip competition will likely intensify, taking on dynamics similar to an arms race, with both powers concerned about relative gains, turning it into a zero-sum game. The U.S. has a cost advantage in reorganizing supply chains due to its network of allies, while China faces increasing isolation, though it will strive for self-sufficiency and attempt to create wedges in U.S. alliances.

Ultimately, dominance in the chip sector will depend not only on technological advancement but also on innovation capabilities, production efficiency, and strategic maneuvering in a complex geopolitical environment. National governments must work closely with corporations to formulate long-term R&D and industrial strategies. As Morris Chang noted, geopolitical challenges like "friend-shoring" and "onshoring," which he never encountered during his tenure, are now realities that current leaders must navigate. Richard Chang's experiences, on the other hand, show that even in the face of sanctions and lawsuits, a strong sense of mission and government backing can foster resilient contenders.

The outcome of this chip war will profoundly influence the global technological landscape and the international balance of power.

The global semiconductor industry often fixates on expensive, advanced processes. However, the latest work by Singhal & Hasan (2026) reminds us that exceptional "architectural innovation" can yield a disruptive competitive advantage.

The value contribution of this work lies in demonstrating a viable path to high-performance phased array systems on a low-cost process (180nm). Its distinct competitive advantage stems not from costly materials or scaling, but from a sophisticated "novel active feed network."

The "phase averaging" principle at the core of this architecture successfully reduced hardware complexity (from N=7 down to N=3+1), leading to a minimal chip area of 5.7 mm². More significantly, the network functions as an "active gain stage" (+18.2 dB) rather than a passive lossy component, achieving "gain integration" at the system level. This unique design allows low power consumption (74.8 mW/channel) and high gain (25.4 dB) to coexist, ultimately achieving a 38° scanning range even under the strict -7dB SLL performance boundary.

The work by Singhal & Hasan (2026) is a classic example of "architecture triumphing over process." This not only challenges the long-held "process-is-everything" industry myth but also signals a potential major breakthrough in the cost structure for fields reliant on phased arrays, such as 5G/6G communications, satellite internet, and autonomous driving radar. It provides a technical blueprint for the commercial mass production of phased array technology and offers a profound extension of thought for the industry: beyond the pursuit of cutting-edge processes, system-level architectural optimization may be the other grand avenue toward technological democratization and cost-effectiveness.

全球半導體產業的焦點，常集中於昂貴的先進製程。然而，Singhal & Hasan (2026) 的最新研究提醒我們，卓越的「架構創新」同樣能帶來顛覆性的競爭優勢。

本研究的價值貢獻，在於揭示了低成本製程（180nm）下，實現高性能相控陣列系統的可行路徑。其明顯的競爭優勢並非依賴昂貴的材料或微縮，而是精巧的「新型主動饋電網路」。

該架構的核心「相位平均」原理，成功將硬體複雜度顯著降低（從 N=7 降至 N=3+1），使晶片面積縮至極小的 5.7 mm²。更重要的是，此網路扮演了「主動增益級」(+18.2 dB)，而非傳統的被動損耗元件，在系統層面實現了「增益整合」的獨特優勢。這使得 74.8 mW/通道的低功耗與 25.4 dB 的高增益得以並存，最終在嚴苛的 -7dB SLL 性能邊界下，仍達成了 38° 的掃描範圍。

Singhal & Hasan (2026) 的成果，是「以架構戰勝製程」的經典範例。這不僅挑戰了長期以來「製程至上」的產業迷思，也為 5G/6G 通訊、衛星互聯網和自動駕駛雷達等依賴相控陣列的領域，帶來了成本結構上的重大突破可能。它為相控陣列技術的商業化量產提供了可行的技術藍圖，更為整個產業帶來深刻的延伸思考：在追求極致製程之外，系統級的架構優化，或許是實現技術普及與成本效益的另一條選擇!

Table 2 from Singhal, N., & Hasan, S. M. R. (2026)

Reference:

Singhal, N., & Hasan, S. M. R. (2026). Low-cost analog CMOS beamformer transmitter with novel active feed network. Microelectronics Journal, 167, 106934. https://doi.org/10.1016/j.mejo.2025.106934

2025年10月9日

Rare Earth Strategy Escalates: The Critical Impact on Global Semiconductor and AI Industries

China's new rare earth control measures, announced by the Ministry of Commerce on October 9, 2025, elevate the strategic significance of rare earth exports to an unprecedented level. The core of this new policy is the expansion of controls from mere "raw material" export to encompass "end-use, technology, and equipment," explicitly targeting cutting-edge technology sectors. Specifically, the R&D and production of 14nm and below logic chips, 256-layer and above memory chips, along with AI technology with potential military uses, will be subject to stringent case-by-case review. Furthermore, foreign-manufactured items "containing Chinese components valued at 0.1% or more" are now regulated, effectively extending China's export controls into the international supply chain hinterland.

The profound impact of this new policy stems from the pivotal role rare earths play in the global supply chain. Rare earth elements (REO), often dubbed the "vitamins of industry," are critical due to their unique magnetic, electric, optical, and catalytic properties. China has long dominated the global rare earth supply, holding approximately 35.2% of global reserves and accounting for over 60% of production, being the only country capable of supplying all 17 rare earth metals. Rare earths are core components for high-performance chips, AI servers, and electric vehicle motors.

For the global semiconductor industry, this move inevitably exacerbates supply chain pressure. Rare earths are extensively used in crucial stages of wafer manufacturing. For instance, cerium oxide particles are the indispensable abrasive medium in Chemical Mechanical Polishing (CMP) slurry, directly affecting wafer planarization and yield. Rare earth elements like scandium are also key doping materials for advanced semiconductor structures (e.g., Aluminum Scandium Nitride alloy). Magnetic components (such as NdFeB rare earth permanent magnets) are utilized in power supply and cooling systems for HPC/AI equipment.

Faced with the potential threats of restricted rare earth sources and rising costs, semiconductor powerhouses like Taiwan must accelerate their response. In the short term, companies should diversify risks through multiple procurement channels and meticulously evaluate the percentage of Chinese rare earth components in their products. In the long term, the strategic focus must shift towards material self-sufficiency, actively investing in rare earth recycling technologies (such as developing urban mining solutions), and seeking material substitution alternatives. This is essential for building a more resilient and secure domestic supply chain to maintain a competitive edge in the international tech race.

稀土戰略再升級：全球半導體與AI產業面臨的關鍵衝擊

中國商務部於2025年10月9日發布的新管制措施，將稀土出口的戰略意義提升至前所未有的高度。這項新政的關鍵在於，管制範圍從單純的「原料」出口，首度擴展到「最終用途、技術與設備」，明確鎖定尖端科技領域。特別是針對14奈米及以下邏輯晶片、256層及以上儲存晶片的研發與生產，以及具潛在軍事用途的AI技術，均需實施嚴格的逐案審批。此外，「含有中國成分價值比例達0.1%以上」的境外製造物項亦被納管，實質上將中國的出口管制延伸至國際供應鏈的腹地。

這項新政的深遠影響，源於稀土在全球供應鏈中的核心地位。稀土元素（REO）因其獨特的磁、電、光、催化性能，被譽為「工業維生素」。全球稀土供應長期由中國主導，其儲量佔全球約35.2%，產量更佔六成以上，是唯一能夠提供全部17種稀土金屬的國家。稀土是高效能晶片、AI伺服器與電動車馬達的核心材料。

對於全球半導體製造業而言，此舉無疑加劇了供應鏈壓力。稀土被廣泛應用於晶圓製造的關鍵環節，例如：氧化鈰顆粒是**化學機械拋光（CMP）**漿料中不可或缺的研磨介質，直接影響晶圓的平坦化和良率。稀土元素如鈧，亦是先進半導體結構（如氮化鋁鈧合金）的關鍵摻雜材料。磁性元件（如稀土永磁釹鐵硼）則用於高效能運算設備的電源供應與冷卻系統。

面對稀土來源受限、成本上漲的潛在威脅，半導體大國如台灣等必須加速應變。短期內，企業應透過多元採購管道來分散風險，並審慎評估其產品中的中國稀土成分比例。長期來看，必須將戰略重心轉向材料自主化，積極投入稀土回收再利用技術（例如發展城市礦山回收），以及尋求材料替代方案，以建立更具韌性與安全性的本土供應鏈，確保在國際科技競賽中維持競爭優勢。

Reference:

• DIGITIMES. (2025). 中國稀土管制首度納入半導體、AI 14奈米晶片、256層記憶體用途將逐案審查

• 陳宥菘. (2025, October 9). 陸稀土出口管制加嚴！「含中國成分境外稀土」也納管陸商務部曝原因. 經濟日報.

• 吳妍. (2025, October 9). 中國擴大稀土管制範圍涵蓋半導體與軍事敏感技術. Yahoo奇摩新聞.

• 楊任軒, 方聖予, 周靜, & 張致吉. (2022, December). 稀土關鍵材料供應鏈危機下的衝擊與因應 (專題報告 2022-03). 財團法人中技社.

2025年9月16日

Just wrapped up an insightful SEMICON Taiwan 2025 forum! My biggest takeaway this year is that the rules of the game are changing. Advanced Packaging is no longer a backup plan for Moore's Law; it has become a co-star, standing on equal footing with—and is arguably a "hotter topic" than—front-end logic.

Synthesizing insights from experts at TSMC, BCG, Yole, and more, here are my key takeaways on Advanced Packaging:

The Age of Turbulence: AI as the New North Star

The forum consistently highlighted that we've entered an "Age of Turbulence," with AI as the undisputed driving force. Dr. Jen-Chieh Chen of TSMC declared 2024 as the "AI era (year one)," projecting the semiconductor market to easily surpass $1 trillion by the end of the decade, fueled by "insatiable demand" for computing. This massive shift is evident in the projected $350 billion+ CapEx by US hyperscalers in 2025.

However, this era isn't just about market growth; it's a fundamental paradigm shift. As Dr. Glyn Wilk of ASM eloquently put it, scaling has moved from "lithography to deposition." We're now in an atomic-scale world where "every monolayer matters," and precision technologies like Atomic Layer Deposition (ALD) and Epitaxy (Epi) are defining the future of transistors.

Advanced Packaging: The Heart of AI Performance

Advanced packaging has ascended from an auxiliary role to a core driver, "equally important" to front-end logic. Here's why:

✨ Key Benefits and Why It Matters

• AI Performance Enabler: As Dr. Chen emphasized, "all AI accelerators on the market today" leverage advanced packaging, such as CoWoS, to integrate high-bandwidth memory (HBM). Without it, the immense computational power of modern AI chips would be unattainable.

• Post-Moore's Law Innovation Engine: When traditional transistor scaling hits the "Scaling Wall," as noted by JT Hsu of BCG, "innovation shifts to packaging and system design." Advanced packaging provides the critical path to bypass physical limits and continuously enhance chip performance, power, and area (PPA).

• Heterogeneous Integration Hub: Future AI systems demand the integration of diverse functionalities, often from different process nodes or even different materials. Technologies like SoIC (3D stacking) allow for vertical integration of logic, while CPO (Co-Packaged Optics) seamlessly integrate optical communication to overcome copper interconnect bottlenecks, as highlighted by Dr. Wilk.

🚧 Challenges & Intricacies

While its benefits are profound, advanced packaging presents significant challenges:

• Extreme Technical Complexity: Gary Huang of Yole Group described it as "very sophisticated." This complexity isn't limited to the packaging itself but extends to stringent upstream requirements for ALD and Epi processes, demanding "atomically abrupt interfaces" and exceptional conformality.

• Immense Supply Chain Pressure: Sharon Hsu of Dell Technologies noted that the rapid growth of AI servers places "tremendous pressure" across the entire supply chain, from material procurement to system integration. This intricate interdependency is a direct consequence of advanced packaging's complexity.

• Cost and Yield Management: Although not explicitly detailed, the complexity of processes, the multitude of materials, and the intricate 3D integration invariably lead to increased costs and significant yield management challenges.

Future Outlook & Strategic Imperatives

The future for advanced packaging is undeniably bright and a central focus:

🚀 Clear Direction: System-Level Integration

The trajectory is clear: towards complete system-in-package solutions. This blueprint includes:

• 3D Vertical Stacking: Through technologies like SoIC, enabling unprecedented transistor density.

• Optical Integration: Integrating CPO and silicon photonics to achieve ultra-high-speed data transfer.

• Integrated Passive Components: Embedding components like Integrated Voltage Regulators (IVR) directly within the package.

Strategic Shifts

• From Foundry to System Foundry: TSMC's strategy signals an evolution from a pure-play wafer manufacturer to a "System Foundry." This means offering integrated solutions encompassing logic, memory, optics, and other functionalities.

• Dual-Engine Strategy: TSMC views both logic and advanced packaging as "equally important" pillars. Dr. Chen aptly characterized logic as the "foundation," with advanced packaging "augmenting it" to reach the next level of performance.

• Taiwan's Strategic Asset: Gary Huang emphasized that Taiwan's resilience in the global supply chain is substantially derived from its "leading technology in packaging," solidifying its role as a crucial geopolitical strategic asset.

Navigating the Future: Resilience and Collaboration

Beyond the technical marvels, the forum consistently brought up the "Age of Turbulence" and the critical need for "resilience." As JT Hsu cited Ayrton Senna, "You cannot overtake 15 cars in sunny weather, but you can when it's raining." This underscores that chaos presents unique opportunities.

For Taiwan, this means addressing internal constraints like land, water, electricity, and manpower, as highlighted by Professor Shieh-Ming Lien. He also underscored that the true threat from political pressures isn't just tariffs, but potential "antitrust laws" and "US technology restrictions" – making strategic cooperation (like potential joint ventures with US customers) vital.

In conclusion, SEMICON Taiwan 2025 conveyed a powerful message: Advanced Packaging is a pivotal enabler for the AI era, its strategic importance elevated to unprecedented heights. Future success belongs to enterprises capable of the deepest and most effective integration of both front-end logic and back-end packaging, all while navigating a complex geopolitical and resource-constrained landscape with robust resilience.

#AdvancedPackaging #Semiconductor #AIChips #SystemIntegration #TSMC

參加完多場 SEMICON Taiwan 2025 論壇，收穫滿滿！今年最深刻的體會是，產業的遊戲規則正在改變。先進封裝（Advanced Packaging）已不再是摩爾定律之後的備案，而是與前端邏輯製程平起平坐、甚至更熱門的主角。

綜合台積電、BCG、Yole 等多位專家的觀點，我整理了幾個關於先進封裝的關鍵洞察：

✨ 為何先進封裝是 AI 時代的核心賦能者？

性能的實現者：若沒有 CoWoS 這類技術整合 HBM，今日 AI 加速器的強大算力將無從發揮。目前市場上「所有的 AI 加速器」都採用了此類技術。

後摩爾定律的引擎：當電晶體微縮面臨「微縮之牆 (Scaling Wall)」，產業的「創新將轉向封裝與系統設計」，以持續提升晶片 PPA (效能、功耗、面積)。

異質整合的樞紐：先進封裝是實現系統級晶片（System-on-Chip）的關鍵，它能將邏輯、記憶體（SoIC）、光學元件（CPO）等不同功能的晶片整合在一起，突破單一晶片的極限。

🚧 挑戰與機會並存

當然，這條路充滿挑戰。先進封裝是「非常精密複雜 (very sophisticated)」的系統工程，對供應鏈管理帶來「巨大的壓力 (tremendous pressure)」。從材料、設備到良率控制，每一個環節都需要整個生態系共同努力。

🚀 未來方向與市場策略

從晶片到系統：台積電的策略清楚揭示，晶圓代工廠的角色正從純粹的晶片製造者，演變為提供整合方案的「系統級代工廠 (System Foundry)」。

雙引擎並進：台積電將邏輯製程視為「基礎 (foundation)」，而先進封裝則是「增強其性能 (augments it)」的關鍵。兩者同等重要，缺一不可。

台灣的戰略資產：台灣在封裝領域的領先技術，已成為其在全球供應鏈中不可或缺的戰略韌性來源。

總結來說，AI 時代的戰爭不僅僅在前端的奈米競賽，更延伸到了後端的立體整合。未來的勝利者，將是那些能夠將這兩者進行最深度、最有效整合的企業。

#先進封裝 #半導體 #AI晶片

2025年9月10日

[Chilly's SEMI Notes] The "Age of Turbulence" Is Here: AI Has Completely Rewritten the Rules of the Semiconductor Game

Fresh from the "Semiconductor Advanced Process Technology Forum," I'm struck by one profound realization: the industry is no longer just discussing "trends." We have fully entered an "Age of Turbulence" driven entirely by AI. This was the collective message from experts at TSMC, ASML, Applied Materials, ASM, Lam Research, and Tokyo Electron.

1. The Insatiable Demand for AI Compute: A Market and Infrastructure Boom TSMC's Dr. Chen aptly declared 2024 as "Year One of the AI Era." This "insatiable demand" for computing power is set to drive the market well past $1 trillion by the end of the decade. Underscoring this, the top four US cloud service providers are projected to spend over $350 billion in capex in 2025 alone—a testament to the infrastructure frenzy underway.

2. The New Paradigm of Scaling: From Lithography to Atomic-Level Craftsmanship For years, "scaling" was synonymous with "advanced lithography." However, as ASM's Dr. Wilk highlighted, starting from the 3nm node, the paradigm has shifted from lithography to deposition. Today, the future of transistors is dictated by the "digital precision" of Atomic Layer Deposition (ALD) and Epitaxy. The phrase "every single atomic layer matters" is now the ground truth.

3. The Vertical Race & Key Technologies: "Building High Rises" on a Chip The evolution from FinFET to Gate-All-Around (GAA) and the future CFET is a technology race akin to "building high rises" on a chip. Several key technologies are now front and center:

• Atomic Layer Deposition (ALD): Critical for solving overlay errors through Area-Selective Deposition (ASD), its application layers have increased 20-fold in 20 years.

• Epitaxy: In GAA, channel quality is no longer defined by etch but by the quality of epitaxial growth, demanding "atomically abrupt interfaces."

• Advanced Packaging: As TSMC's Dr. Chen precisely put it: "Logic as foundation, packaging as augmentation." Every AI accelerator on the market uses CoWoS, and the future lies in system-level packages integrating SoIC, HBM, and CPO.

4. New Battlegrounds & Bottlenecks: Interconnects, Materials, and Energy BCG's JT Hsu pointed out that copper interconnects have hit their limit. "The experiment is over" for Photonics; it's now entering full commercialization. Meanwhile, supply chain vulnerabilities—from critical materials (like T-glass shortages) to the "energy wall" (data centers may consume as much electricity as Japan by 2030)—are becoming critical constraints.

Conclusion: The finish line is no longer defined by scaling alone, but by a total war of materials science, system architecture, and advanced packaging. We are at the dawn of a massive transformation defined by atomic-scale engineering, system-level integration, and geopolitics.

A sincere thank you to Dr. Chin-Hsiang Lin-TSMC, Dr. Chia-Hsin Lee-Brewer Science Taiwan, Dr. Chien Chen-TSMC, Pin-Ting Wang-ASML, Dr. Gaurav Thareja-Applied Materials, Dr. Glen Wilk-ASM, Mr. David Easterday-Lam Research, and Dr. Peter Loewenhardt-Tokyo Electron for their invaluable insights.

#Semiconductors #AI #AdvancedProcess #TSMC #AdvancedPackaging #CoWoS #GAA #CFET #ALD

【Chilly的SEMI觀察筆記】AI驅動的「動盪年代」：半導體遊戲規則已徹底改變

昨日剛參加完「半導體先進製程科技論壇」，學習新知的興奮仍持續著。這場由台積電、ASML、應用材料、ASM、Lam Research、Tokyo Electron 等巨頭的專家們共同擘劃的未來藍圖，給我最深刻的感受是：半導體產業不再只是討論「趨勢」，而是已經全面進入由 AI 驅動的「動盪年代 (Age of Turbulence)」。

1. AI 算力的無底洞：市場規模與基礎建設的狂潮 台積電的 Dr. Chen 開宗明義地宣告，2024 年是 AI 時代元年。這股「永不滿足的算力需求 (insatiable demand)」正驅動市場在本年代末輕鬆突破 1 兆美元。美國四大雲端服務巨頭預計在 2025 年投入超過 3500 億美元的資本支出，為這場基礎建設狂潮提供了最堅實的註腳。

2. 微縮的新典範：從微影轉向原子級工藝 過去，我們認為「微縮」等同於「更先進的微影」。但 ASM 的 Dr. Wilk 明確指出，自 3 奈米起，微縮的典範已從微影轉向了沉積 (Deposition)。如今，是原子層沉積 (ALD) 和磊晶 (Epitaxy) 在原子層級的「數位精準度 (digital precision)」決定了電晶體的未來。「每一個原子層都至關重要」，這句話已成為新時代的真理。

3. 垂直競賽與關鍵技術：在晶片上「蓋高樓」 從 FinFET 到環繞式閘極 (GAA)，再到未來的 CFET，這場技術競賽就像在晶片上「蓋高樓 (building high rises)」。要實現此目標，以下技術已成核心：

• 原子層沉積 (ALD): 透過區域選擇性沉積 (ASD) 解決疊對誤差，其應用層數在過去 20 年暴增 20 倍。

• 磊晶 (Epitaxy): GAA 的通道品質不再由蝕刻決定，而是由磊晶生長的「原子級陡峭介面」所定義。

• 先進封裝: 台積電 Dr. Chen 精準定位：「邏輯為基石，封裝為增強 (Logic as foundation, packaging as augmentation)」。所有 AI 加速器都採用 CoWoS，未來整合了 SoIC、HBM 與 CPO 的系統級封裝將是主流。

4. 新的戰場與瓶頸：互連、材料與能源 BCG 的 JT Hsu 指出，銅導線已達極限，光子學 (Photonics) 的「實驗已經結束」，正全面商業化。同時，供應鏈的脆弱性也浮上檯面，從關鍵材料（如 T-glass 短缺）到能源牆（2030 年資料中心耗電量將相當於整個日本），都成為了限制發展的關鍵。

總結： 這場競賽的終點線不再由單一的微縮技術決定，而是材料科學、系統架構與先進封裝的總體戰。我們正站在一個由原子級工藝、系統級整合與地緣政治共同定義的巨大變革起點。

#半導體 #AI #先進製程 #台積電 #TSMC #先進封裝 #CoWoS #GAA #CFET #ALD

半導體先進製程科技論壇

2025-09-09 | 上午 9:00 - 下午 5:00

地點: 南港展覽館2館 7樓-701C

主題: AI-Driven Technologies: Powering the Next-Gen Semiconductor Era

Advised by: SEMI IC Committee

主辦單位: SEMI Taiwan

Reference: 김범근. (2025, August 22). 한투證 “SK하이닉스·삼성전자 비중확대…HBM 경쟁우위·엔비디아 수혜”. 이투데이. Retrieved from https://www.etoday.co.kr/news/view/2499090

Drawing Source: Chillyin rewrote this piece, drawing from Trendforce, Korea Investment & Securities. Image retrieved from etoday Aug 22, 2025).

In the era of advanced AI computing, High-Bandwidth Memory (HBM) is no longer just a critical component; it has become the strategic high ground that defines the future frontiers of computational power. The core of recent market dynamics revolves around the fierce competition in HBM technology, particularly the next-generation HBM4, among the three giants: SK hynix, Samsung Electronics, and Micron. The outcome of this race will directly impact the performance and supply chain structure of NVIDIA's next-gen AI accelerator, the "Rubin" platform.

Value Contribution & Key Reporting The value of HBM lies in its ability to solve the "memory wall" bottleneck faced by AI chips. By vertically stacking DRAM and connecting it to the processor with an ultra-wide interface, HBM achieves bandwidth and efficiency unparalleled by traditional memory, making it indispensable for Large Language Model (LLM) training and inference. According to the Korean media outlet etoday and consolidated market intelligence, the HBM3E market, currently dominated by SK hynix, is facing a significant shift. Reports indicate that Samsung's HBM4 samples have passed NVIDIA's validation, with mass production potentially starting by the end of the year. This poses a direct challenge to SK hynix, which has long been the exclusive high-end supplier for NVIDIA. The focus of this competition is not only on production timelines but also on technological roadmaps. Both Samsung and SK hynix plan to use foundry processes for HBM4's base die to integrate more logic functions and unlock customization potential, whereas Micron may stick with its existing DRAM process. This divergence signals that HBM is evolving from a standardized memory product into a "customized" era of deeper integration with AI processors.

Extended Thinking Insights from the provided technical papers reveal that HBM's evolution extends beyond a mere race for bandwidth and capacity. For instance, Processing-in-Memory (PIM) architectures like SparsePIM enable HBM to perform specific tasks, such as sparse matrix-vector multiplication, directly within the memory, drastically reducing data movement latency and power consumption. Concurrently, new co-processor concepts like the High-bandwidth Processing Unit (HPU) demonstrate how HBM can offload memory-intensive workloads from the GPU to enhance overall system efficiency. However, as system complexity grows, reliability emerges as a new challenge.

The "fail-slow" phenomenon—where a device's performance degrades gradually rather than failing completely—is critical for maintaining the stability of large-scale AI clusters, necessitating new detection frameworks.

In conclusion, the HBM war has evolved from a simple contest of capacity and speed into a multi-dimensional competition encompassing process strategy (Foundry vs. DRAM Process), architectural innovation (PIM, Co-processing), and system reliability (Fail-Slow Detection). The company that can master next-generation technology and build a robust ecosystem with leaders like NVIDIA will secure the most advantageous core position in the construction of the global AI infrastructure.

在高階AI運算時代，高頻寬記憶體（HBM）已不僅是關鍵零組件，更是定義未來算力邊界的戰略高地。近期市場動態的核心，圍繞著SK海力士、三星電子與美光三巨頭在HBM技術，特別是次世代HBM4上的激烈角逐。這場競爭的勝負，將直接影響NVIDIA下一代AI加速器「Rubin」平台的效能與供應鏈格局。

價值貢獻與重點報導 HBM的價值在於它解決了AI晶片面臨的「記憶體牆」瓶頸，透過垂直堆疊DRAM並以超寬介面與處理器相連，實現了傳統記憶體無法比擬的頻寬與效率，是大型語言模型（LLM）訓練與推論不可或缺的動能。根據韓國媒體《이투데이》及綜合市場訊息，目前由SK海力士主導的HBM3E市場正迎來變局。

報導指出，三星的HBM4樣本已獲NVIDIA驗證，最快可能在2025年底量產，這無疑是對長期獨家供應NVIDIA高階產品的SK海力士發出最直接的挑戰。這場競賽的焦點不僅在於量產時程，更在於技術路線的選擇：三星與SK海力士紛紛計畫採用晶圓代工（Foundry）製程生產HBM4的基礎晶粒（Base Die），以整合更多邏輯功能與客製化潛力；而美光則可能維持現有的DRAM製程。此一分野，預示著HBM將從標準化記憶體，走向與AI處理器更深度整合的「客製化」時代。

延伸思考 從提供的技術文獻中，我們能窺見HBM的發展不僅止於頻寬與容量的競賽。例如，透過處理器內存儲（Processing-in-Memory, PIM）架構（如SparsePIM），HBM能直接在記憶體內部執行稀疏矩陣運算等特定任務，大幅降低資料搬運的延遲與功耗。同時，高頻寬處理單元（HPU）等新型協同處理器概念，也展示了如何利用HBM分擔GPU的記憶體密集型工作，提升整體系統效率。然而，隨著系統複雜度提升，可靠性成為新的挑戰。

「Fail-Slow」現象，即裝置性能緩慢下降而非完全失效，對於維持大規模AI叢集的穩定至關重要，這也催生了新的檢測框架需求。

總結而言，HBM的戰爭已從單純的產能與速度之爭，演變為一場涵蓋製程策略（Foundry vs. DRAM Process）、架構創新（PIM、協同處理）與系統可靠性（Fail-Slow Detection）的多維度競賽。誰能率先掌握次世代技術並與NVIDIA等領導者建立穩固的生態系，誰就將在全球AI基礎設施的建構中，佔據最有利的核心位置。

2025年9月9日

"Fail-slow" is a specific failure mode that manifests as performance degradation rather than a complete system crash. It can occur in various components, including disks, SSDs, CPUs, memory, and networks. Unlike "fail-stop" faults, which have clear failure criteria (e.g., a software crash), fail-slow issues are transient and imprecise, making it difficult for engineers to diagnose or reproduce the root cause based on experience.

In High Bandwidth Memory (HBM), the common root causes of fail-slow faults can be summarized as follows:

1. Hardware Defects and Architectural Complexity

2. Fault-Tolerant Design of Memory Chips

3. Product Quality Disparities

4. Environmental Factors and Human Error

5. Scheduling Strategy Issues

6. Unknown Causes

Image Source: Generated by the author/Chilly Chiou using Google AI Studio (Gemini model) based on a specific prompt (Sep 6, 2025).Hardware Defects and Architectural Complexity

Accumulation of Minor Defects: During operation, memory chips can accumulate minor defects from process imperfections, runtime disturbances, or harsh environments. Affected memory cells may not fail completely but will exhibit intermittent errors and reduced access speeds, degrading overall system performance.

Complex 3D-Stacked Architecture: Beyond inheriting error patterns from traditional DRAM, HBM's complex 3D-stacked architecture (e.g., packaging, Through-Silicon Vias or TSVs) introduces new potential points of failure.

Operating Conditions and Structural Impacts: Studies show that factors like rising temperatures, lower voltages, package joints, TSV structures, and disturbance issues like RowHammer can all affect HBM reliability and lead to new faults.

Fault-Tolerant Design of Memory Chips

Many memory chips feature fault-tolerant designs that mask partial errors by discarding bad addresses. However, as errors accumulate over time, the available memory size decreases. This leads to a higher cache miss rate, and performance degrades due to more frequent page swapping.

Product Quality Disparities

Quality can vary between memory chips from different manufacturers and even between different batches from the same manufacturer. Some studies indicate that certain memory products are more prone to errors.

Environmental Factors and Human Error

Environmental Conditions: For example, devices deployed at high altitudes may be exposed to more cosmic rays, leading to frequent multi-bit errors.

Human Error: Loose hardware connections can cause significant performance degradation, which is often resolved after an operator re-inserts the memory card.

Scheduling Strategy Issues

Ill-Implemented Scheduling: Although HBM hardware has fixed clock cycles for read/write operations, inefficient software scheduling strategies can still create congestion between the host and the device.

Uneven Resource Utilization: Unevenness among different operators in the scheduling process can lead to low HBM utilization at certain times. This can cause throughput to drop to less than half of its normal level for periods as long as 20 minutes.

Unknown Causes

In some cases, memory modules exhibit severe performance degradation only under specific workloads but return to normal under other benchmarks. The exact causes remain unclear but may be attributed to operator scheduling, hardware mechanisms, or other yet-to-be-discovered factors.

「Fail-slow」是一種特殊的故障模式，它不會造成系統完全崩潰，而是以性能下降的形式出現，可能發生在磁碟、固態硬碟、CPU、記憶體和網路等多種組件中。與「Fail-stop」（例如軟體崩潰）這類有明確失敗標準的故障相比，「Fail-slow」的特性是瞬態且不精確的，使工程師難以根據經驗判斷或重現問題的根源。

在高頻寬記憶體（HBM）中，導致「Fail-slow」故障的常見原因可歸納如下：

硬體缺陷與架構複雜性

微小缺陷累積：記憶體晶片在運作中，會因製程瑕疵、運行干擾或惡劣環境累積微小缺陷。這些受影響的記憶體單元不會完全失效，但會出現間歇性錯誤和存取速度變慢的問題，進而拖累整個系統的性能。

複雜的3D堆疊架構：HBM除了繼承傳統DRAM的錯誤模式外，其複雜的3D堆疊架構（如封裝、矽穿孔TSV）也引入了新的故障風險。

操作條件與結構影響：研究顯示，溫度升高、電壓降低、封裝接點、TSV結構，以及RowHammer等干擾問題，都會影響HBM的可靠性並可能導致新的故障。

記憶體晶片的容錯設計

許多記憶體晶片具備容錯設計，在發生部分錯誤時會自動遮蔽，將不良位址拋棄。但隨著時間推移，當錯誤持續增加，可用記憶體容量會減少，導致快取未命中率（Cache Miss Rate）提高，系統因更頻繁的頁面交換而性能下降。

產品品質差異

不同製造商、甚至同一製造商不同批次生產的記憶體晶片都存在品質差異。部分研究指出，某些記憶體產品更容易出現錯誤。

環境因素與人為錯誤

環境條件：例如，部署在高海拔地區的設備，可能因暴露於更多的宇宙射線而導致頻繁的多位元錯誤。

人為疏失：鬆脫的硬體連接也可能導致顯著的性能下降，這類問題通常在操作員重新插拔記憶體後解決。

排程策略問題

不佳的排程實作：雖然HBM硬體層面的讀寫操作有固定的時脈週期，但在主機與裝置之間，不佳的軟體排程策略仍可能引發擁塞問題。

資源利用不均：由於排程過程中不同運算子（Operator）的負載不均，可能導致HBM在某些時段利用率過低，甚至使吞吐量在長達20分鐘內降至正常水準的一半以下。

未知原因

在某些情況下，記憶體模組僅在特定工作負載下出現嚴重性能下降，但在其他基準測試下則恢復正常，其確切原因仍待釐清，可能與操作員排程、硬體機制或其他尚未發現的因素有關。

Reference:

Xu, Z., Zhang, Y., & Shen, Z. (2025). A Fail-Slow Detection Framework for HBM Devices. In 30th Asia and South Pacific Design Automation Conference (ASPDAC ’25). ACM.

2025年8月31日

Reference: Huang, C. H. (2017). 2017 Smart Robot Industry Foresight and Trend Analysis. Mechanical Industry Magazine, 406, 29-37.

The "Developmental Evolution of Robot Products" chart reveals a clear path for robots from "dedicated automation" to "general intelligent agents." This is not just a change in product form but a leap in core technology and market value.

Stage One: Industrial Robots (Dedicated Automation)

Process Evolution: This stage begins with the most fundamental "automation," with the core being the precise movement of mechanisms and joints. Industrial robots (such as robotic arms) are designed to perform specific, highly repetitive tasks, such as welding and material handling in the automotive or 3C manufacturing industries. Key Value: The value lies in "predictable precision execution." They can continuously perform pre-set dynamic tasks, accurately controlling horizontal or vertical movements, significantly enhancing production efficiency and quality in structured environments. Taiwan's Industrial Opportunity: Taiwan already has a deep foundation in this stage. Leveraging its advantages in precision machinery, motors, controllers, and automation systems integration, Taiwanese manufacturers play an indispensable role in the key components and systems integration of industrial robots.

Stage Two: Service Robots (Perception & Interaction)

Process Evolution: Robots begin to incorporate "perception" capabilities, enabling environmental awareness and navigation through sensors (like Lidar and cameras). This allows robots to move beyond factories and into semi-structured environments such as hospitals, hotels, and homes to provide services like guidance, food delivery, and cleaning. Key Value: The value proposition upgrades to "autonomous execution of minimal risk strategies." They can not only perform complete tasks but also have a preliminary understanding of the environment, conduct simple task reasoning, and engage in basic human interaction, demonstrating initial autonomy. Taiwan's Industrial Opportunity: Taiwan's strength in the Information and Communications Technology (ICT) industry comes into play at this stage. From high-precision sensors and chip design to software algorithms, these are Taiwan's strong suits. Developing service robots helps extend the hardware manufacturing advantage into the market for integrated hardware-software application services.

Stage Three: Humanoid Robots (Cognitive Decision-Making & Generalization)

Process Evolution: This is the ultimate goal of the evolution. On the foundation of powerful "perception," robots are endowed with "cognition" and "decision-making" capabilities, equipping them with "Embodied Intelligence." Through fusion with Large Language Models (LLMs), humanoid robots can understand complex commands and autonomously make decisions and execute complex tasks in unstructured, unknown environments. Key Value: The core value lies in "versatility" and "adaptability." Because their form is similar to humans, they can seamlessly integrate into social environments designed for humans, breaking down application barriers between industrial, commercial, and domestic settings, addressing social issues like labor shortages, and becoming the best vehicle for realizing the value of AI. Taiwan's Industrial Opportunity: This represents a key opportunity for Taiwan's industrial upgrading.

• Core Hardware: Humanoid robots have extremely high requirements for high-performance motors, precision reducers, sensors, and dexterous hands, presenting an extended opportunity for Taiwan's precision manufacturing.

• AI Computing Power: As the computational core of the AI brain, Taiwan's semiconductor industry chain (from chip design to manufacturing) holds an absolute global advantage and is the key engine driving the development of humanoid robots.

• Systems Integration: By combining Taiwan's existing hardware and software integration capabilities and investing R&D resources to enhance the fusion of AI algorithms with the robot body, there is an opportunity to leap from a component supplier to a core system provider in the global humanoid robot supply chain.

2025年8月23日

The "Chip War" in Hydrogen: Where Trillion-Dollar Global Subsidies Meet Semiconductor Hard Power

A recently circulated blueprint of global hydrogen policies (as shown in the table 1) clearly reveals an undeniable trend: the world's major economies are betting on hydrogen at an unprecedented scale. From the US$8 billion for Hydrogen Hubs in the U.S. and the €12 trillion investment under the EU's REPowerEU plan, to China's "Medium and Long-Term Plan for the Development of the Hydrogen Energy Industry," this is not just a race for energy transition. It's a new geopolitical game centered on technological dominance.

However, when we discuss electrolysis, storage, and transportation, we often overlook the true "brain" and "nervous system" behind it all—semiconductors.

🚀 The "Hidden Champion" of the Hydrogen Race: Power and AI Chips

Every segment of the hydrogen economy is heavily reliant on advanced semiconductor technology:

1. Efficient Production (Electrolysis): Green hydrogen production requires splitting water via electrolyzers. The key to maximizing efficiency and minimizing energy loss lies in sophisticated power management. This is the primary battlefield for third-generation semiconductors like Silicon Carbide (SiC) and Gallium Nitride (GaN), whose superior performance under high-voltage, high-frequency conditions is crucial for boosting electrolysis efficiency.

2. Smart Storage & Transport: Whether it's high-pressure gas or cryogenic liquid storage, a vast number of sensors are needed to monitor pressure, temperature, and leaks, all managed by microcontrollers (MCUs) for real-time, stable control.

3. AI-Driven Grid Management: Green hydrogen production depends on renewables, which are intermittent. How do we manage power dispatch, predict generation capacity, and optimize storage and demand response? This requires a smart grid driven by AI algorithms, supported by immense demand for cloud and edge computing chips.

🧠 A Leadership Psychology Perspective on National Strategy: A Test of "Delayed Gratification"

Governments investing billions, even trillions, are not seeking short-term returns. This is the ultimate test of a nation's leadership in practicing "delayed gratification." Leaders must persuade the public and industries to invest today for a cleaner future that may only be fully realized in a decade or two.

This also explains the subtle differences in national strategies:

• The U.S. Model (Venture Capital): By establishing "Regional Clean Hydrogen Hubs," the U.S. adopts a venture capital-like approach, fostering regional competition and innovation.

• The EU Model (Regulatory Push): The EU drives the market with clear production targets (20 million tons by 2030), regulations, and standards.

• The China Model (Ecosystem Building): China emphasizes creating a complete industrial value chain, from production to application, showcasing a state-led, systematic approach.

👇 Implications for Taiwan: Not Just a Player, but an Enabler

As the world positions itself for the "new gold rush" of hydrogen, Taiwan's opportunity extends beyond being a mere user. Our greatest advantage lies in mastering the critical technologies that power this entire revolution.

Taiwan's semiconductor value chain—from IC design and foundry services to packaging and testing—is perfectly positioned to provide the complete "brain" and "nervous system" for the hydrogen economy. This is not just a massive emerging market; it is a golden opportunity for Taiwan to elevate its role in the global tech supply chain from a "hardware manufacturer" to an "enabler of the future energy architecture."

The question is, are we ready for it?

氫能的「晶片戰爭」：當全球兆元補貼賽道，遇上半導體硬實力

最近一張全球氫能政策的藍圖（如上所述 Table 1）提及多國的能源政策，全球能源的趨勢：世界主要經濟體正以前所未有的規模，將賭注押在氫能上。從美國的80億美元氫能中心、歐盟的12兆歐元投資，到中國的《氫能產業發展中長期規劃》，這不僅是一場能源轉型的競賽，更是一場圍繞著科技主導權的「新地緣政治賽局」。

然而，當我們談論電解水、儲存、運輸時，常常忽略了這一切背後真正的「大腦」與「神經系統」——半導體。

🚀 氫能賽道的「隱形冠軍」：功率與智慧晶片

氫能經濟的每一個環節，都高度依賴先進半導體技術：

1. 高效電解 (Production): 綠氫的生產需要透過電解槽將水分解。要實現最大效率、最小化能源損耗，關鍵在於精密的電源管理。這正是第三代半導體，如碳化矽 (SiC) 和氮化鎵 (GaN) 的主戰場。它們在高電壓、高頻率下的卓越表現，是提升電解效率的核心。

2. 智慧儲運 (Storage & Transport): 無論是高壓氣態儲存還是低溫液態儲存，都需要大量的感測器 (Sensors) 來監測壓力、溫度與洩漏，並透過微控制器 (MCU) 進行即時、穩定的控制。

3. AI 驅動的電網管理 (Grid Management): 綠氫的生產依賴再生能源，而再生能源具有間歇性。如何調度電力、預測產能、優化儲存與需求響應？這需要一個由 AI 演算法驅動的智慧電網，背後是龐大的雲端運算與邊緣運算晶片需求。

🧠 從領導力心理學看國家戰略：這是一場「延遲滿足」的考驗

各國政府投入數十億、甚至上兆的資金，追求的並非短期回報。這是一場考驗國家領導層「延遲滿足」能力的極致展現。領導者必須說服民眾與產業，為了一個十年、二十年後才能完全實現的潔淨未來進行投資。

這也解釋了各國戰略的微妙差異：

• 美國模式 (Venture Capital): 透過建立「區域潔淨氫能中心」，更像是一種創投模式，鼓勵區域競爭與創新。

• 歐盟模式 (Regulatory Push): 透過設定明確的產能目標（2030年2,000萬噸），以法規和標準來驅動市場。

• 中國模式 (Ecosystem Building): 強調建立完整的產業鏈，從生產到應用，展現了國家主導、系統化佈局的決心。

👇 對台灣的啓示：不只是玩家，更是賦能者 (Enabler)

當全球都在為氫能這座「新金礦」佈局時，台灣的機會不僅僅是成為氫能的使用者。我們最大的優勢，在於我們掌握了驅動這一切的關鍵技術。

台灣的半導體產業鏈，從 IC 設計、晶圓代工到封裝測試，完全有能力提供氫能經濟所需的全套「大腦」和「神經」。這不只是一個新興的龐大市場，更是台灣在全球科技供應鏈中，從「硬體製造者」提升為「未來能源架構賦能者」的絕佳機會。

問題是，我們準備好了嗎？